Custom templates can be created for non-standard patterns. Creation of pattern is basically selecting a template, entering a couple of vital parameters, drawing the silkscreen, and launching automatic pad renumbering.

Circle, lines (headers, DIP), square (QFP), matrix (BGA), rectangle (RQFP), and zig-zag standard templates. More than 140000 components in standard libraries.ĭraw patterns with various types of shapes, pads, holes, and dimensions. Importing libraries from different EDA formats. BSDL import, bulk pin naming, and pin manager tools for pins and buses. Manage component libraries and create single- or multi-part components by selecting a template and its dimensions, defining visual and electrical pin parameters, setting up a Spice model, and attaching pattern with a 3D model to finalize component creation.

Design rule check with in-depth detailing and net connectivity verification procedures are available. The board can be previewed in 3D and exported to STEP format for mechanical CAD modeling. DRC also checks length and phase tolerances for differential pairs and controls signal synchronization for nets and buses (including layer stackup and bonding wire induced signal delays). When routing with real-time DRC, the program reports errors on the fly before actually making them. Design requirements are defined by net classes, class-to-class rules, and detailed settings by object types for each class or layer. DipTrace Schematic has ERC verification and Spice export for external simulation.Įngineering tool for board design with smart manual routing, differential pairs, length-matching tools, shape-based autorouter, advanced verification, layer stackup manager, and wide import/export capabilities. Cross-module management ensures that principal circuits can be easily converted into a PCB, back-annotated, or imported/exported from/to other EDA software, CAD formats and net-lists. Screenshot of Schematic Capture in DipTrace v3 (2016)Īdvanced circuit design tool with support of multi-sheet and multi-level hierarchical schematics that delivers a number of features for visual and logical pin connections.

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